On the Design of a Parallel Algorithm for VLSI Layout Compaction
نویسنده
چکیده
In this paper we present the essential features of an approach for the design of a parallel algorithm for the layout compaction problem. We begin with a formulation of the problem presented by Yoshimura in [4]. This formulation is in terms of the dual transshipment problem. Our approach t o the solution of the dual transshipment problem involves repeated applications of three basic steps, namely, testing feasfblllty, shortest-path computations and performing concurrent pivot operations. Our discussion is in terms of marked graph concepts and results presented in [5], [B]. Our approach can also be used in the study of the relative placement problem discussed in [7] by Mlynski and Weiss.
منابع مشابه
Integrated VLSI layout compaction and wire balancing on a shared memory multiprocessor: evaluation of a parallel algorithm
We first present a unged formulation to three problems in VLSI physical design: Layout compaction, Wire balancing and Integrated layout compaction and wire balancing problems. The aim of layout compaction is to achieve minimum chip width. Whereas wire balancing seeks to achieve minimum total wire length, integrated layout compaction and wire balancing seeks to minimize wire length maintaining t...
متن کاملEfficient Cellular Automata Algorithms for Planar Graph and VLSI Layout Homotopic Compaction
One-dimensional homotopic compaction is defined as; In a given routable layout, a layout of minimum width is reachable by operations that can move each module horizontally as a unit, also deform lines maintaining their connections and maintain their routability. This paper exploits the nature of parallelism of this problem and introduces an efficient cellular automata algorithm for homotopic co...
متن کاملMinimizing total wire length during 1-dimensional compaction
Minimizing the total wire length is an important objective in VLSI layout design. In this paper we consider the problem of minimizing the total wire length during I-dimensional (I-D) compaction. Assume we are given a layout. containing nh horizontal wires, nlJ vertical wires, and rectilinear polygonal layout. components c.omposed of 7lr vertical edges. We present an O(n/, ·nlogn) time algorithm...
متن کاملA Tunned-parameter Hybrid Algorithm for Dynamic Facility Layout Problem with Budget Constraint using GA and SAA
A facility layout problem is concerned with determining the best position of departments, cells, or machines on the plant. An efficient layout contributes to the overall efficiency of operations. It’s been proved that, when system characteristics change, it can cause a significant increase in material handling cost. Consequently, the efficiency of the current layout decreases or is lost and it ...
متن کاملLayout - S ynthesis Techniques for Yield Enhancement
Several yield enhancement techniques are proposed for the last two stages of VLSI design, i.e., topological/symbolic and physical layout synthesis. Our approach is based on modiications of the symbolic/physical layout to reduce the sensitivity of the design to random point defects without increasing the area, rather than fault tolerance techniques. A layout compaction algorithm is presented and...
متن کامل